A/D converters are essential elements to many integrated circuit applications, such as automatic control, data acquisition, and data processing systems, wherein they provide interfaces for converting real-word parameters to digital data adapted for processing by logic circuits, memories, and microprocessors. A/D converters of the successive approximation type are generally preferred, because they combine good speed of execution (200 to 500 ns per bit) with low cost, ease of manufacture (single-chip LST), and good accuracy, and can operate with up to 12 bits in current implementations.
A/D converters of the successive approximation type are included in the line catalogs of all leading manufacturers of semiconductor products. The architecture of a successive approximation A/D converter usually includes a comparator, a digital-to-analog (D/A) converter, and control logics, as shown in FIG. 1. This logic is often referred to as Successive Approximation Register (SAR). A SAR functions to determine the value of each bit in a sequential manner according to the comparator output. A SAR initiates the conversion cycle by putting the most significant bit (MSB) of a word equal to 1 and all the other bits to 0 (trial). This digital word is applied to the D/A converter, which will generate an analog signal whose value is one half the conversion range, Vref/2, and which is compared with the input Vin. If the comparator output is high, then the control logics will set the MSB at 1, or at 0 (decision) if the output is low. At this point the value of the MSB has been determined. The approximation process is continued with the application of a digital word to the D/A converter with an MSB having its exact value and the second trial bit at 1, and all of the remaining bits at zero. The D/A output is again compared with the input: if the comparator output is high, the second bit is set at 1, otherwise at 0, and so on to the least significant bit, LSB, of the word. The contents of the successive approximation register reflect the digital result of the conversion performed.
A SAR is a sequential finite state machine (MSF) which generates the sequence of states shown in the following table (where, for simplicity, the instance of a number N=8 of bits is assumed). Consider the evolution of the sequence in the table: step 1 forces the initialization configuration. Throughout the following steps, three actions are possible on the individual bit: forcing the trial 1, result of the decision from the comparator, storing the previous value.
______________________________________ Conversion Comparative step D/A input word output ______________________________________ 0 1 0 0 0 0 0 0 0 a.sub.7 1 a.sub.7 1 0 0 0 0 0 0 a.sub.6 2 a.sub.7 a.sub.6 1 0 0 0 0 0 a.sub.5 3 a.sub.7 a.sub.6 a.sub.5 1 0 0 0 0 a.sub.4 4 a.sub.7 a.sub.6 a.sub.5 a.sub.4 1 0 0 0 a.sub.3 5 a.sub.7 a.sub.6 a.sub.5 a.sub.4 a.sub.3 a.sub.2 1 0 a.sub.2 6 a.sub.7 a.sub.6 a.sub.5 a.sub.4 a.sub.3 a.sub.2 1 0 a.sub.1 7 a.sub.7 a.sub.6 a.sub.5 a.sub.4 a.sub.3 a.sub.2 a.sub.1 0 a.sub.0 result a.sub.7 a.sub.6 a.sub.5 a.sub.4 a.sub.3 a.sub.2 a.sub.1 a.sub.0 -- ______________________________________
The successive approximation algorithm by which the table can be described is the following: taking a conversion step whichever, the value at the next step for each bit k of the word input to the D/A converter can be the value of:
the bit on the left (k+1), if all the bits of lower significance (k-1, k-2, . . . , 0) than this bit, and the bit itself, have a value of "0"; PA1 the comparator output, if this is "1" and all the least significant bits thereof have a value of "0"; PA1 the bit itself, if at least one of the least significant bits has a value of "1".
By implementing this algorithm through a suitable logic network, the same storage elements (flip-flops) that hold the result of the conversion can be used to encode the 2N possible states of the finite state machine MSF.
An n-bit SAR usually has a serial input (comparator output) and an n-bit parallel output (result of the A/D conversion), as shown in FIG. 1.
Certain applications of A/D converters require a serial I/O (input/output) configuration, e.g., for specific serial data exchange standards providing an interface which can be easily serviced by certain processor families. Thus, to obtain a serial output, a parallel input/serial output (PISO) shift register is usually employed which takes n clock periods to shift the result of an n-bit A/D conversion. This use of the A/D converter involves two registers (SAR and PISO) and requires 2n clock periods (n clock periods to obtaining the result of the successive approximation conversion, and n clock periods, called result "latency", for outputting the result).
The underlying technical problem of this invention is to provide a SAR which can handle a serial data output directly, without any additional registers. In particular, a low latency for the result outputting (a single clock period) is sought. This problem is solved by a shift register as previously indicated and further described below.
Additional objects, advantages, novel features of the present invention will become apparent to those skilled in the art from this disclosure, including the following detailed description, as well as by practice of the invention. While the invention is described below with reference to preferred embodiment(s), it should be understood that the invention is not limited thereto. Those of ordinary skill in the art having access to the teachings herein will recognize additional implementations, modifications, and embodiments, as well as other fields of use, which are within the scope of the invention as disclosed and claimed herein and with respect to which the invention could be of significant utility.